Transistors are generally fabricated by forming gate stacks on a semiconducting substrate. A gate stack typically includes a layer of polycrystalline silicon (poly-Si) on a gate dielectric. The poly-Si layer may be doped in order to set the work function of the poly-Si and reduce its resistivity. This technique of gate stack fabrication, however, may result in the formation of a relatively thick depletion layer. The thick depletion layer may cause a reduction in the overall gate capacitance, which may decrease the drive current of a device, resulting in the degradation of device performance. Thus, it may be challenging to dope poly-Si to a sufficiently high level to minimize depletion.
Known techniques to reduce this effect of the depletion layer may include increasing the doping level of the poly-Si. This known technique, however, may be difficult to implement because there is a limit to the number of carriers that can be attained by doping. Another known technique may involve using a metal layer instead of the doped poly-Si layer to increase the overall gate capacitance and to reduce the formation of the depletion layer. This technique, however, may be unsatisfactory because the metal may react with adjacent layers when exposed to high temperatures during a fabrication flow. The effect of the reaction of the metal with an adjacent layer may be reduced by using a thick metal layer or by limiting the thermal budget of the device, both of which may also affect the size and performance of the semiconductor device. Consequently, known techniques for fabricating a semiconductor structure may be unsatisfactory in certain situations.